Automating Layout of Reconfigurable Subsystems for Systems-on-a-Chip
نویسندگان
چکیده
Automating Layout of Reconfigurable Subsystems for Systems-on-a-Chip by Shawn A. Phillips Chair of the Supervisory Committee: Professor Scott Hauck Electrical Engineering As technology scales, engineers are presented with the ability to integrate many devices onto a single chip, creating entire systems-on-a-chip. When designing SOCs, a unique opportunity exists to add custom reconfigurable fabric, which will provide an efficient compromise between the flexibility of software and the performance of hardware, while at the same time allowing for post-fabrication modification of circuits. Unfortunately, manually generating a custom reconfigurable fabric would make it impossible to meet any reasonable design cycle, while adding considerably to design costs. The goal of the Totem Project is to reduce the design time and effort in the creation of a custom reconfigurable architecture. This thesis is focused on automating the layout generation of custom reconfigurable devices for systems-on-a-chip. Towards this end, we present three methods, namely the Template Reduction, Circuit Generator, and Standard Cell Methods. The Template Reduction Method begins with a full-custom layout as a template that is a superset of the required resources, and removes those resources that are not needed by a given application domain. The Circuit Generator Method takes advantage of the regularity that exists in FPGAs using circuit generators to create the custom reconfigurable devices. Finally, the Standard Cell Method automates the creation of circuits by using a standard cell library that has been optimized for reconfigurable devices.
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